1. Field of Invention
The present invention relates to a packaging process of a light-emitting diode (LED) device. More particularly, the present invention relates to a bumping process for a flip chip package structure of a light-emitting diode.
2. Description of Related Art
Recently, the light-emitting diodes (LEDs) employing gallium nitride-based (GaN-based) semiconductor materials such as gallium nitride (GaN), gallium aluminum nitride (GaAIN), and gallium indium nitride (GaInN), have been weighed to be potential. The III-nitride compounds have wide band energy gap and the light emitted by such compound ranging from the ultraviolet light to the red light, the wavelength of the which covers almost the entire waveband of the visible light.
The luminescence efficiency of the GaN-based LED device is determined by the two following main factors: (1) internal quantum efficiency of an active layer of the GaN-based LED device; and (2) light extraction efficiency of the GaN-based LED device. The internal quantum efficiency of the active layer is not only determined by the epitaxial quality, but also determined by the structure of the active layer. The loss of the light emitted by the active layer mainly results from the internal total reflection phenomenon within the GaN-based LED device, and the light extraction efficiency can be improved by decreasing the light loss. Furthermore, in the GaN-based LED device with a sapphire substrate, the anode and the cathode are both formed on the same surface of the active layer and will block out the light emitted from the underlying active layer. Due to limitations of the wire bonding technologies, the area of each bonding pad formed on the anode or the cathode must be larger than the minimum bonding area to ensure the bonding strength between wires and bonding pads. For example, the minimum diameter or the minimum width of each bonding pad is about 80 micrometers.
As described above, due to the limitations of the required minimum bonding areas and the shadow effects, the packaging process employing the wire bonding technology faces the above problems. Alternatively, a flip chip packaging process for the LED chip is developed. In the flip chip packaging process, bumps are formed on the anode and the cathode of a LED chip (the bumping process), and then the LED chip is flipped so that the anode and the cathode thereon con be electrically connected with a substrate through the bumps. Since the internal quantum efficiency of the active layer will not be degraded by thermal issues, the GaN-based LED devices fabricated by the flip chip packaging process provide enhanced light extraction efficiency and better heat dissipation performance. Therefore, the GaN-based LED devices with the flip chip package structures may become the future mainstream products.
FIGS. 1A to 1H are cross-sectional views of a conventional bumping process of light emitting diodes. Referring to FIG. 1A, firstly, a wafer 100 having a plurality of LED chips 102 is provided. Each LED chips 102 comprises a plurality of electrodes 110 (anode and cathode) and a passivation layer 120. The passivation layer 120 covers the surface of each LED chip 102 but exposes the electrodes 110. The passivation layer 120 con be made of inorganic compounds, for example, silicon nitride, silicon oxide or phosphosilicate glass (PSG) etc. Alternatively, the passivation layer 120 can be made of organic compounds, for example, polyimide etc.
Referring to FIG. 1B, a metal layer 130 is formed over the passivation layer 120 by sputtering or evaporation.
Referring to FIG. 1C and FIG. 1D, a photo-lithography/etch process is performed after the metal layer 130 is formed. Specifically, a photoresist layer 140 is formed on the metal layer 130, and then a photo-mask is provided above the photoresist layer 140 so that the pattern of the photo-mask can be transferred to the photoresist layer 140 through exposure and development to form a plurality of openings 142. The openings 142 expose the metal layer 130 located above the electrodes 110. Referring to FIG. 1E and FIG. 1F, a gold bump 150 and a solder layer 152 are sequentially formed in each opening 142 by electroplating gold (Au), tin (Sn) or lead(Pb). The gold bump 150 is formed directly on the metal layer 130, while the solder layers 152 formed on the gold bumps 150 are used for electrically connecting with a package substrate (not shown).
Referring FIG. 1G and FIG. 1H, the photoresist layer 140 is removed from the surface of the metal layer 130, and then a portion of the metal layer 130, which is not covered by the gold bumps 150, is removed by dry or wet etching. The metal layer 130 under the gold bumps 150 is remained as an under bump metallurgy (UBM) layer 132. Furthermore, a reflow process is performed to form Au/Sn or Pb/Sn eutectic between the bumps 150 and the solder layer 152, wherein the eutectic is used for enhancing adhesion characteristics between the solder layer 152 and a package substrate (not shown).
A plurality of bumps con be formed on the wafer by electroplating or evaporation, and the height of bumps formed on the wafer usually ranges from about several micrometers to more. However, the cost of the bumps formed by evaporation is quite high, and it is difficult to precisely control the height and the composition of the bumps. Even though, the cost of the bumps formed by electroplating is relatively lower, the cycle time and the total costs of the bumping process using electroplating are comparable due to necessary procedures, equipments and efforts of bumping process shown in FIG. 1A to FIG. 1H. In addition, since one layer can only be formed of a single metal material by electroplating, the flexibility of bumping process using electroplating is tightly limited and unable to meet requirements of various package structures.